1. Technical Field
The present invention relates in general to a method of measuring the bandwidth of a signal channel that carries an electrical signal. More particularly, the present invention relates to a single port measurement method to determine the bandwidth of a test signal channel of a wafer test system, the channel being provided through a probe card, where the probe card is used to test integrated circuits (ICs) on a wafer.
2. Related Art
A wafer test system includes a number of test channels for carrying test signals to and from ICs on a wafer. Bandwidth testing of the probe card or test interface is performed to assure the integrity and frequency response of the test interface. Many test systems employ Time Domain Reflectometry (TDR) to measure and calibrate the path delay of the interface to the Device Under Test (DUT) when the interface is open circuit or otherwise not in contact with the DUT. As presently deployed however, the TDR measurement does not directly give an indication of the channel Bandwidth. Direct use of the reflected signal rise time is not practical because impedance mismatches and discontinuities in the interface create reflections and amplitude variations that adversely affect the true bandwidth measurement.
FIG. 1 shows a block diagram of a test system using a probe card for testing ICs on a semiconductor wafer. The test system includes a test controller 4 connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18. The prober 10 includes the probe card 18 supporting probes 16 which contact ICs formed on the wafer 14.
In the test system, test data is generated by the test controller 4 and transmitted on individual test channels through the communication cable 6, test head 8, connectors 24, probe card 18, probes 16 and ultimately to ICs on the wafer 14. The probe card 18 serves to link each channel to a separate one of the probes 16. Test results are then provided from ICs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test controller 4. Once testing is complete, the wafer is diced up to separate the ICs.
FIG. 2 is a cross sectional view showing details of typical components of the probe card 18. The probe card 18 is configured to provide both electrical pathways and mechanical support for test channels connecting through probes 16 to contact ICs on a wafer. The probe card electrical pathways are provided through a printed circuit board (PCB) 30, an interposer 32, and a space transformer 34. Channels from the test head 8 are directed to individual pins of multi-pin connectors 24 typically connected around the periphery of the PCB 30. Traces 40 then continue the channels paths from connectors 24 through the PCB 30 to contact pads on the opposing side of the PCB 30 spaced to match the routing pitch of pads on the space transformer 34. The interposer 32 includes a substrate 42 with spring probe electrical contacts 44 disposed on both sides. The interposer 32 continues to provide the channel paths from the pads on the PCB 30 to contact pads on a space transformer 34. Traces 46 in the space transformer 34 distribute or “space transform” the channel lines from the interposer to spring probes 16 configured in an array. The space transformer 34 with embedded traces and connected probes is referred to as a probe head.
Mechanical support for the electrical components is provided by a back plate 50, bracket 52, frame 54, leaf springs 56, and leveling pins 62. The back plate 50 is connected by screws 59 to the bracket 52 and PCB 30. The leaf springs 56 are attached by screws 58 to the bracket 52. The leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52. The frame 54 then supports the space transformer 34. Leveling pins 62 complete the mechanical support, and are adjusted so that brass spheres 66 provide a point contact with the space transformer 34. Leveling pins 62 are adjustable to level the space transformer 34 and assure all the probes 16 will make contact with a wafer.
Although FIG. 1 provides an exemplary wafer test system configuration, it is contemplated that other test systems may be served by the present invention. For instance, the probe interface might be replaced with one or more sockets for testing of packaged or bare devices. Such test board systems for testing singulated devices are often referred to as “load boards”. Similarly, although FIG. 2 illustrates one configuration for connecting test channels of a wafer test system to contacts that can connect to ICs on a wafer, other configurations for channels can be provided. For example, although probes 16 are shown as wire type spring probes, other electrical contacts such as pogo pins, cobra probes, lithographically formed spring probes, or conductive bumps might be used. Similarly, the interposer 32 can be replaced with wire bonds or a removable connector. For convenience, components of the overall test system of FIG. 1 and probe card of FIG. 2 will be referenced subsequently.
After manufacture of a probe card, testing is performed to determine the electrical and mechanical properties of the probe card. Signal integrity testing provides a determination of operation bandwidth specifications of the probe card channels, as well as the detection of both hard (manufacturing) and soft (design) errors in the test interface.
FIG. 3 illustrates a typical test configuration of test system components to determine the bandwidth of individual channels. As shown, the test components include a test system analyzer 70, which may be the tester system 4 of FIG. 1 itself, or a separate testing device such as a vector network analyzer (VNA) used to determine the S parameters of a system. A first port 72 of the test system analyzer 70 is connected to at least one test channel in the cable 6 that is provided through test head 8 (as illustrated by line 73). The test channel then proceeds through probe card 18 and one of its probes 16 to one of a number of pads 74 on a PCB 76. The PCB 76 is specifically created for calibration of the probe card 18 and includes pads 74 for connection of channels back through the test system analyzer through a cable 77. The cable 77 is connected back to a second port 78 of the test system analyzer 70. The through path between the first and second ports 72 and 78 of the test system analyzer enable a signal to be transmitted to determine parameters of the test system.
Measurement of a test signal using the test setup of FIG. 3 enables a simple determination of bandwidth. Bandwidth is specified as the frequency at which a sinusoidal input signal voltage is attenuated to 70.7% of its original amplitude, also known as the −3 dB or half power point. FIG. 4 shows a measured response for a 100 MHz test channel line.
Another way to indirectly measure bandwidth of a channel is to measure the rise time of a signal through the channel and correlate the rise time to bandwidth. One measure of the rise time of an input signal is the time for a signal to transition from 10% to 90% of the maximum signal amplitude. With the 10% to 90% rise time, bandwidth can be calculated using the formula: bandwidth×rise time=0.35. Thus the bandwidth measured is defined as: bandwidth=0.35/(Tr10-90), where the measured rise time from 10% to 90% is labeled (Tr10-90). Determination of bandwidth using a 10% to 90% rise time measurement is illustrated in FIG. 5.
Bandwidth can be determined from a rise time over a smaller portion of a signal transition, such as a 20% to 80% range. For a 20% to 80% rise time, bandwidth is typically calculated using the formula: bandwidth×rise time=0.22. Thus, for measurements based on a 20% to 80% rise time, the bandwidth is defined as: bandwidth=0.22/(Tr20-80), where the measured rise time is labeled (Tr20-80).
It is also well known that the overall rise time of a system labeled (Toa) is the square root of the sum of the squares of the individual component rise times (T1, T2, . . . ) represented as follows:Toa=√{square root over (T12+T22+T32)}To isolate the bandwidth measurement of the probe card alone, test measurements can be made to determine the rise time through components without the probe card 18 between the test ports of the calibration device 70. The equation for Toa shown above can then be used to separate out the rise time measurement of the probe card from the overall rise time Toa.
Due to changes in the channel bandwidth after multiple contacts of the test probes to ICs on wafers, it may be desirable to verify that the bandwidth of each channel is meeting specification before the probe card is used to test DUT specifications. With the probe card installed in a test system for testing ICs on wafers, it is typically inconvenient to reconfigure the test system to provide a two port measurement setup as shown in FIG. 3 to enable bandwidth verification for all channels of the probe card or DUT interface. It would be desirable to provide a more convenient method for determining the bandwidth of the individual channels of the test system.